In general, a DRAM cell includes one transistor and one capacitor, which are disposed on an active region. The DRAM cell uses the capacitor to store data in response to a “high-state” or “low-state.” Accordingly, the DRAM cell includes an area occupied by the capacitor.
Recently, a DRAM cell that does not need a capacitor has been proposed. This DRAM cell is referred to as a single transistor floating-body DRAM cell (hereinafter, a ‘single transistor DRAM cell’). The single transistor DRAM cell includes a floating body. The floating body of the single transistor may be disposed on a silicon-on-insulator (SOI) substrate. As a result, the body of the single transistor is electrically isolated from adjacent bodies and floated. Since the single transistor DRAM cell stores data in the floating body, it does not require a capacitor. Therefore, a cell region may be reduced so that the DRAM cell can be improved in integration density.
FIG. 1 is a cross-sectional view of a conventional single transistor DRAM cell.
Referring to FIG. 1, the single transistor DRAM cell includes an SOI substrate 1. The SOI substrate 1 includes a semiconductor substrate 2, a buried insulating layer 3 disposed on the semiconductor substrate 2, and a floating body 4 disposed on the buried insulating layer 3. The buried insulating layer 3 may be formed of silicon oxide. A pair of source and drain regions 5 and 6 are disposed on both sides of the floating body 4. An insulated gate electrode 7 is disposed on the floating body 4. A gate insulating layer 8 is interposed between the insulated gate electrode 7 and the floating body 4. As a result, the floating body 4 is electrically isolated by the buried insulating layer 3, the gate insulating layer 8, and the source and drain regions 5 and 6.
Hereinafter, a write operation of a conventional single transistor DRAM cell having the above-described construction will be described. During the write operation, the DRAM cell can store data in the following process. First, the source region 5 is grounded. A word line program voltage equal to or higher than a threshold voltage is applied to the gate electrode 7. Also, a bit line program voltage is applied to the drain region 6. In this case, the bit line program voltage is higher than the word line program voltage. When the bit line program voltage is Vd, the word line program voltage may be Vd/2. As a result, impact ionization occurs around the drain region 6. When the transistor is an NMOS transistor, hot carriers, i.e., holes, are accumulated in an active region 9 of the floating body 4 due to the impact ionization. The threshold voltage of the transistor depends on the number of the holes accumulated in the active region 9 of the floating body 4. The number of the holes accumulated in the active region 9 of the floating body 4 can be controlled by adjusting the amount of current flowing between the source and drain regions 5 and 6.
Hereinafter, a read operation of the conventional single transistor DRAM cell will be described. During the read operation, the DRAM cell can read data in the following process. First, the source region 5 is grounded. A word line read voltage lower than the word line program voltage is applied to the gate electrode 7. In this case, a bit line read voltage is applied to the drain region 6. As a result, the amount of current flowing between the source and drain regions 5 and 6 depends on the number of holes stored in the active region 9 of the floating body 4. That is, data stored in the single transistor DRAM cell can be read by sensing the amount of current flowing between the source and drain regions 5 and 6.
The above-described single transistor DRAM cell is also described in U.S. Pat. No. 6,861,689 to Burnett.
In the conventional single transistor DRAM cell having the above-described construction and function, a short channel effect (SCE) may occur with the downscaling of DRAM memory devices. As a result, the operating characteristics of the DRAM cell may still deteriorate.
Moreover, in order to increase the integration density of DRAM memory devices, the DRAM memory devices are being scaled down or reduced in number. However, a reduction in the number of the DRAM memory devices may result in a decrease of memory storage capability.